- Data in the core’s registers are sent to the RAM when a thread is taken away from the core.
- The context of the new thread is checked for in L1 first, then L2, L3 and RAM
- Reasoning,
- There are more software threads than there are hardware threads in reality
- Thus if we move the thread 1’s context from registers to L1 cache then context might have to be moved to L2 as more threads come into play and then to L2, L3 as more threads come.
- Thus when thread 1 gets the core back, it’s highly likely that it’s context have to be fetched from RAM
- Given this is the case, it makes me sense to use the entirety of L1 cache, L2 cache and so on for the thread that is currently executing
- cache eviction
Note
Historically registers have always existed in cpus. Caches were added later when cpu frequencies started increasing faster than RAM frequencies.